1. Field of the Invention
The present invention relates to an apparatus such as a game apparatus which is operated by a control of a central processing unit (CPU) for executing a control program.
2. Description of the Prior Art
An apparatus operating on the power supply from a power source generally uses the commercial alternating current (AC) power supply. Since it is inconvenient that a function of such an apparatus is started again from the beginning when the power supply is started again after the commercial AC power supply is cut due to power failure or after the apparatus is turned off, the function being performed at the time when the power is cut is backed up so that the function is continuously performed when the power supply is restored. During such a backup period, a battery is used as the power source. In order to reduce the power consumption of the battery to the minimum, it is preferable to back up only the irreducible minimum of the circuits in the apparatus with the battery. Therefore, in the case of an apparatus operated by a central processing unit (CPU), a memory such as a random access memory (RAM) is provided to maintain a program or a data activated while the power is being supplied at the point of time when the power is cut. The program or the data is successively stored in the RAM in advance while the power is being supplied. In a conventional arrangement of FIG. 1, an address command data from a CPU 30 is decoded firstly by a first circuit 31 and then by a second circuit 32, thereby obtaining an address of a read only memory (ROM) 33. It is impossible to use an output of the first circuit 31 without any processing. This output is not usable until it is further decoded by the second circuit 32. In this conventional arrangement, at least two ICs (31 and 32) are used. This is because the circuit is constructed by using a general purpose IC since no integrated circuit (IC) specifically used to decode an address command data from a CPU is provided. A third circuit 34 is used to supply a selection signal from the CPU 40 to a RAM 35. To the RAM 35, a new program address is written in accordance with the progress of the program. With respect to the power source, power from an AC adapter 36 is supplied to the CPU 30, to the first and second circuits 31 and 32 and to the ROM 33. Selection between the power from the AC adapter 36 and the power from a battery 37 is automatically made by diodes D1 and D2. The selected power is provided to the third circuit 34 and to the RAM 35. In this case, when power is output from the AC adapter 36, the diode D1 is ON and the diode D2 is OFF, so that power from the AC adapter 36 is selected. When no power is output from the AC adapter 36, the diode D1 is OFF and the diode D2 is ON, so that power from the battery 37 is selected.
In this conventional arrangement, however, since a plurality of circuits are used to decode the addressing data from the CPU 30 (i.e. the addressing data is decoded by the first and second circuits 31 and 32) to thereby obtain the selection signal (address) of the ROM 33, the processing line to the ROM 33 is long. As a result, the signal delay between the input and the output increases. This is because there are stages of gates constituting the first and second circuits 31 and 32 provided in series and because delay is caused by distributed capacity of a connecting line between ICs. A signal for selecting the RAM 35 provided through the third circuit 34 is delayed in a similar manner.
If the delay of the selection signal increases, the reading of a program data at the ROM 33 and the reading and writing at the RAM 35 will be delayed, so that the timing of the entire game apparatus does not concur with that of the CPU 30. Moreover, since the diodes D1 and D2 which are discrete parts are used to select the power source, a power loss is caused due to a voltage drop by the diodes D1 and D2. Further, because of the diodes D1 and D2 and the circuits 31, 32 and 34, the number of parts and the space on the circuit board occupied by those parts increase.